1. Technical Field
The present application generally relates to three-dimensional NAND Flash memory and, more specifically, to systems and methods of programming memory cells in an array to reduce the influence of program disturb and back-pattern effects.
2. Related Art
NAND Flash memory is a nonvolatile memory that is used in a wide range of applications including mobile phones, digital cameras, and solid-state hard drives. The high storage density of NAND Flash memory, especially when compared to NOR Flash memory, has played a large role in its market penetration. This storage density is achieved in part through the use of strings of memory cells connected in series between a ground line and bit lines, which reduces the number of metal contacts required. These strings are commonly called “NAND strings” due to their resemblance to NAND gates. Each memory cell within a NAND string can be addressed by a word line that the memory cell shares with neighboring cells of other NAND strings. In the past, NAND Flash memory has been implemented as a two-dimensional (planar) array defined by word lines and bit lines that intersect perpendicularly, with the memory cells being formed at those intersections.
The NAND string topology has been further developed to achieve still greater storage density. Such efforts have lead to the development of three-dimensional (3D) NAND Flash memory, in which memory cells are stacked vertically on top of one another.
FIG. 1 shows a schematic diagram illustrating a prior 3D NAND Flash array, as well as various transistors used for control. This figure shows four pages 150, 151, 152, 153 (Page 0 to Page 3), which contain a total of eight NAND strings 110. Each NAND string 110 includes a plurality of memory cells, such as the memory cell 112. Each memory cell can be addressed using at least one of the bit lines 140, 141 (BL0 and BL1), at least one of the string select lines 130, 131, 132, 133 (SSL0 to SSL3), and at least one of the word lines 120, 121, 120n (WL0 to WLn). The bit lines 140, 141 may connect to the memory planes 190, 191 defined in different depths of the array structure, such that the memory planes associated with different bit lines may be stacked on top of one another in a z-direction 184. In the embodiment shown in FIG. 1, the bit line 140 (BL0) accesses the plane 190 (Plane 0) and the bit line 141 (BL1) accesses the plane 191 (Plane 1), which is above the plane 190. Furthermore, the bit lines 140, 141 may each be provided at opposite sides of the array structure.
String select lines 130, 131, 132, 133 may be connected to string select transistors 135, which are formed in string select structures on opposite sides of the array structure. These string select transistors connect the array structure to on-chip sense circuitry (not shown) attached to each bit line 140, 141. Each page may be associated with a unique string select line. As shown in the figure, the page 150 (Page 0) is addressed by the string select line 130, the page 151 (Page 1) is addressed by the string select line 131, the page 152 (Page 2) is addressed by the string select line 132, and the page 153 (Page 3) is addressed by the string select line 133. This allows an SSL signal travelling on a given string select line to select a given page (e.g., a stack) of memory cells, effectively setting an “x” coordinate in an x-direction 180. It should be further noted that each page may comprise multiple NAND strings 110, and each NAND string 110 may have an associated string select transistor 135.
The string select transistors 135 connected to even pages 150, 152 may form a first string select structure on one side of the array, and the string select transistors 135 connected to odd pages 151, 153 may form a second string select structure on the opposite side of the array.
The word lines 120, 121, 120n may be connected to gates of the memory cells. Accordingly, a WL signal may address a given memory cell within a selected NAND string, thereby setting a “y” coordinate in a y-direction 182.
Accordingly, each cell within the 3D NAND Flash array may effectively be addressable through “x,” “y,” and “z” coordinates. More specifically, the cells are addressable through signals on the control lines, and they may be addressed for read, program, and erase operations thereby. For example, the memory cell 112 may be addressed by sending and/or receiving signals on the string select line 133, the word line 120n, and the bit line 140. Control signals on unselected lines may additionally be required to perform a given operation.
Ground select lines 160, 161 (GSL(even) and GSL(odd)) may be used to connect and disconnect even and odd pages from common source lines 170, 171 (CSL). In some embodiments, common source lines 170 and 171 are connected together.
It should be noted that the orientations of strings in adjacent pages alternate between bit-line-end-to-source-line-end and source-line-end-to-bit-line-end, which results in the positions of the string select structure (which connects the array to the bit lines) and the common source line physically alternating between even pages and odd pages. For example, on even pages 150, 152, the word line 120 (WL0) is the nearest word line to the common source line 170. However, on odd pages 151, 153, the same word line 120 is the farthest from the common source line 171. Related U.S. Pat. No. 8,503,213 provides further detail into this topology, as well as the reasoning behind it, and is incorporated herein by reference for these and all other purposes. This structure results in a few notable features and consequences.
As indicated by the dashed lines in FIG. 1, the number of word lines may vary based on design considerations. While FIG. 1 shows four pages and two bit lines, the number of pages and bit lines may also vary based on design considerations.
While 3D NAND Flash provides numerous benefits, such as allowing for greater scalability in memory density, it provides new challenges as well. For example, the conventional programming techniques generally applied to 2D NAND Flash arrays may not be as effective when directly applied to 3D NAND Flash arrays. These 2D techniques involve sequentially programming the memory cells, for example, starting with the cell nearest the common source line and finishing with the cell nearest the string select line. This is typically achieved by programming all cells associated with a given word line (e.g., a complete row spanning multiple pages) simultaneously. Accordingly, each row is iterated through until the final row (e.g., the row nearest the string select line) is reached and programmed.
However, employing a similar strategy with the above-described 3D NAND Flash array yields numerous problems, such as read verification issues due to the back-pattern effect in half of the pages. Further issues of program disturb may occur as well.
To understand why these issues occur, it is helpful to understand the physical mechanisms behind information storage. The “memory” of memory cells is often provided through their having an adjustable threshold voltage (Vt). A memory controller may set the Vt of a given cell through program operations and erase operations, and the controller may evaluate the Vt of the cell through a read operation.
In the context of single-level cell (SLC) NAND Flash memory, a programming operation may increase a cell's Vt value above a predetermined boundary value, which allows the cell to store a digital value of “0.” Similarly, an erase operation may decrease the cell's Vt value below the boundary value, which allows the cell to store a digital value of “1.” During a subsequent read operation, the Vt value may be compared to the boundary value, which would allow the stored digital value to be determined as either a “0” or a “1.”
Multi-level cell (MLC) NAND Flash memory expands upon these principles to provide more than one bit in each cell. This is accomplished by utilizing more than one boundary value. For example, three boundary values may be chosen, and Vt may be compared to these boundary values. This effectively provides for four different scenarios, which may represent the digital values of “00,” “01,” “10,” and “11.” Thus, two bits may be stored in each cell. The number of boundary values can be further increased to enable additional bits to be stored in each cell.
As mentioned above, issues can arise when 2D NAND Flash programming techniques are directly applied to 3D NAND Flash arrays. For example, the programmed and erased Vt values may be systematically disturbed. Accordingly, the threshold voltage (Vt) distributions within the memory cells representing a given bit or bits can be widened. When these Vt distributions widen, Vt readings for adjacent bits begin to overlap more frequently, and discerning the stored digital values becomes more challenging. This is especially important in MLC NAND Flash, where the allowable Vt margins between adjacent bits are generally less than those of SLC NAND Flash. Once the number of incorrect readings exceeds a system's tolerance, which is provided in part by error correcting code (ECC), a memory block may fail. It is therefore highly desirable to tighten the Vt distributions of the programmed memory cells to improve reliability and performance, while also increasing the associated process window.